PCI: quirks: work around VL805 firmware ASPM meddling#6790
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P33M merged 1 commit intoraspberrypi:rpi-6.12.yfrom Apr 15, 2025
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PCI: quirks: work around VL805 firmware ASPM meddling#6790P33M merged 1 commit intoraspberrypi:rpi-6.12.yfrom
P33M merged 1 commit intoraspberrypi:rpi-6.12.yfrom
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Certain versions of the VL805 firmware manipulate the endpoint Link Control register to toggle ASPM on/off based on workload, but these versions also report 0 in the Device Capability Acceptable Latency field leaving the RC with ASPM disabled. As it turns out, this EP has a broken L0s implementation so a) override L1 latency to a sensible value and b) mask L0s. Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
pelwell
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See: raspberrypi/linux#6790 kernel: fixup! mmc: sdhci-of-dwcmshc: define sdio timeout clocks See: raspberrypi/linux#6788 kernel: ARM: dts: Include symbols in the CM0 dtb See: raspberrypi/linux#6779
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See: raspberrypi/linux#6790 kernel: fixup! mmc: sdhci-of-dwcmshc: define sdio timeout clocks See: raspberrypi/linux#6788 kernel: ARM: dts: Include symbols in the CM0 dtb See: raspberrypi/linux#6779
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See https://forums.raspberrypi.com/viewtopic.php?t=386386
This has probably been broken on every Pi4/400 with any of the later releases of the VL805 firmware - I'm pretty sure early ones didn't do this. But we no longer ship those in rpi-eeprom and I'm not going to spend time going round the loop with VIA for an update. So a software quirk it is.